Web 51 - RTL8019AS Packet Driver |
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Implementation of packet transmission is very simple. Since the device does not contain a FIFO fot the entire packet and transmits from memory through a DMA channel, it is necessary to wait for transmission to end before constructing another packet in RTL's memory. Another option would be to alternate between two transmit buffers, transmitting a packet from one of them and constructing a packet in the other one. However, even in this case we have to wait sometimes for current transmission to finish. The following code fragment ensures just that:
;************************************************************* ;*** S E N D P A C K E T ** ;************************************************************* ;************************************************************* ;** wait for end of previous transmit ;** tx_wait:First, set a timeout to avoid freezing. Value is chosen so that the packet is either transmitted in full or thrown away as undeliverable.
MOV DPTR,#-40982 ;max coll time = 1024*7 Ethernet slot units (51.2us) tx_wait1:Read the transmission status bit in a loop. If there is no transmission, end the loop.
ISAIN EN_CMD JNB BIT_TRANS,end_tx_wait INC DPTR MOV A,DPH ORL A,DPLAlternatively, end the loop if timeout occurs.
JNZ tx_wait1 ;;Transmit, with error ;; set errors flag... end_tx_wait: RETIf there's no transmission going on, construct a packet to be transmitted in RTL's memory. Include a required Ethernet header with source and destination MAC addresses and packet length. The following code transmits the packet.
;************************************************************* ;** send packet ;** ;input: R6R7 Transmit Byte Count send_pkt:First, to be sure, wait for previous transmission to finish.
; Wait for end of previous transmit ACALL tx_waitThen, check the result of last transmission. If error, set appropriate bits for software handling of transmission error.
; Check for recent TX completions in the interrupt status register ISAIN EN0_ISR ; Interrupt status reg ANL A,#ENISR_TX_ERR+ENISR_TX ; Pending Tx interrupts? JZ tx_idle ; No, Go on new Tx ; JNB BITISR_TX_ERR, XmitFrameNoErr ;; Transmit, with error ;; set errors flag... ;XmitFrameNoErr:If a transmission occured, read detailed completion status and store or handle it.
ISAIN EN0_TSR ; Read Transmit status reg ;; save transmit status...As a final step of processing of previous transmission, acknowledge interrupt from the transmitter.
; Acknowledge the TX interrupt ISAOUT EN0_ISR, #ENISR_TX_ERR+ENISR_TX ; Interrupt status reg ; Set Transmitter Interrupt, with/no errorBefore transmission, verify allowed packet length. First, check if it is less or equal to the maximum 1500 data bytes + 14 header bytes. Throw away longer packets.
tx_idle: MOV A,R7 ; Is packet too large ? ADD A,#LOW(-GIANT-1) MOV A,R6 ADD A,#HIGH(-GIANT-1) JNC XmitNoGiant ;; set errors flag... RETThen, make sure the packet is at least 46+14 bytes long.
XmitNoGiant: MOV A,R6 ; Is the frame long enough ? JNZ XmitNoRunt MOV A,R7 ADD A,#-RUNT JC XmitNoRuntIf shorter, stretch it to the minimal allowed size (fill in with junk from previously transmitted packets, undefined values).
;; MOV R6,#HIGH(RUNT) ; Stretch frame to minimum allowed MOV R7,#LOW(RUNT)Finally, tell RTL the length of the packet and its location in memory(*). Then, start transmission.
XmitNoRunt: BEGINPORTDATA PORTDATA EN0_TCNTHI+portind,AR6 ; High byte of tx byte count PORTDATA EN0_TCNTLO+portind,AR7 ; Low byte of tx byte count PORTDATA EN0_TPSR,NE_START_PG ; Transmit starting page ; First page of TX buffer PORTDATA EN_CMD, EN_PAGE0+EN_NODMA+EN_TRANS+EN_START ; Remote DMA, Transmit a frame, ; Start the chip, clear reset ENDPORTDATA RETPacket Driver RTL8019AS, Part 3
(*) Since version 1.13, memory structure has been modified to support more transmission buffers. Transmission buffer address is no longer a constant; therefore, the above fragment has been modified in the current version.
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