Web51 Hardware
Web51 Hardware |
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Web51 hardware was designed with concern for costs. The goal was to design a low-cost device for telemetry.
Download all documentations & datasheets in .PDF files - Download page - Web51 Hardware docs.
Basic characteristics of Web51 Hardware:
Compact version 3 is based on the prototype. Hobbyists can get the RTL 8019AS from a network interface card; however, it is not easy to remove the chip.
The schematic shows that version 3 has a simple power source, RS232 circuits and EEPROM in addition to the CPU and network controller. Power supply uses a 7805 stabilizer and needs an external adapter. RS-232 converter supports simple HW handshake - RTS/CTS. EEPROM is designated for actual WWW pages, and now even CGI scripts. Final version uses a 89C8252 which can be serially programmed in-system (ISP). PFL34 has all the necessary signals, including I2C for other peripherals.
Ethernet controller - IC2 (RTL 8019) in minimal connection, configured in jumper mode. Resistor R7 switches the controller to 8-bit mode upon reset.
LEDs D3 and D4, connected through R5 and R6, visualize the Ethernet communication. D3 indicates a packet being received, D4 signals a collision. So far we were unable to accomplish dual function - LINK and CRS indication - without using a configuration EEPROM.
Controller has a separate crystal oscillator, consisting of xtal Q2 and capacitors C7 and C8.
The RTL8019AS is used in minimal circuit, that is without external EEPROM 93C46 that usually holds configuration, MAC address, etc. Our solution partially stores these data directly in CPU firmware (MAC address) and partially implements them by switching the controller to "jumper" mode. There are 16 "jumpers", most of them are shared with another signal. Sharing principle is simple. During reset, when signals normally used as outputs are in high impedance, it is possible to set the configuration simply with resistor voltage dividers. Dividers make use of 100K resistors embedded in the device structure and "jumpers" that connect to +5V through external 10K resistors. This way we specify the address of boot ROM, base I/O address, IRQ, and media type. Defaults with no jumpers are:
- boot ROM (BS4..BS0 = 00000) - disabled
- base I/O adresa (IOS3..IOS0 = 0) - 300h
- interrupt (IRQ2..IRQ0 = 0) - IRQ 2/9
- medium (PL1..PL0 = 0) - TP/CX auto detect with 10BaseT link test turned ON
- PnP switch state is uninteresting since the chip is switched to jumper mode by JP=1. AUI switch toggles between AUI/BNC during autodetection and is also uninteresting. The entire design is built upon these defaults; they were even adhered to on the prototype.
Integral part of the Web 51 board. Entire circuitry is strictly symmetrized.
The most complicated part is the 10BaseT transceiver. RTL8019AS contains all digital and analog circuits, except I/O filters and isolating transformers. Therefore, an external hybrid filter/transformer is needed - 20F001N is recommended.
Schematic of 20F001N :
The circuit contains a pair of low-pass filters at 17 MHz and two isolation transformers. This removes higher harmonics that are caused by the digital nature of the circuit and need to be removed to make the signal as sinusoidal as possible. Then, the UTP cable carries only useful signal, with as little noise as possible.
The Micronet network interface board contains a similar hybrid FC-22 (produced by GTS). Compared to Realtek's demo board, this hybrid has an impedance matching and filtering circuit added, consisting of R3/C5 and R4/C6. Input circuits are strictly symmetrized. Capacitors C1 to C4 ground the centers of isolating transformers for AC signal and suppress asymmetric noise.
Detailed information about Ethernet is in a separate part of this documentation.
In the transmitter, the signal passes through RC pairs R3/C5 and R4/C6 that match the impedance and do basic filtering of the output signal. Then the signal passes through a hybrid filter described in the previous part to the output connector CON2.
Received signal comes from connector CON2 through a hybrid filter directly into the controler. Termination at the controller side is ensured by R1 and R2. Their impedance should be half of the line impedance, that is 100R/2 = 50R.
Capacitors C1 to C4 suppress asymmetric noise and ground the centers of isolation transformers for AC signals. Capacitor C16 connects the grounds of Web 51 and the UTP interface for AC signals.
Onboard power supply is based on the standard 7805 stabilizer. Supply voltage from a "wall adapter" comes through connector CON4 to diode D5 (any small rectifying type) that protects the entire board from reversed polarity. Electrolytic capacitor C101 filters the supply voltage. Since version 3.1, near the connector are positions for two diodes that can be used to specify the polarity.
7805 is used in a standard circuit, C102 and C103 decouple the stabilizer circuit, D7 protects the stabilizer should the input voltage drop below output level. C104 is the main filtering capacitor. SMD ceramic capacitors C105 and C106 decouple the CPU supply and Ethernet controller supply. Decoupling capacitor C108 is either ceramic, or better, of a special noise suppressing type.
In the simplest version, the processor is reset by D6 and C11 only. C11 resets the processor at power-on. D6 discharges C11 if the device is reset by a short disconnection of the power supply. We found out that it is not advisable to rely on the resistor embedded in the processor and that an external resistor of about 10K should be connected in parallel to D6.
Since version 3.1, standard RESET circuit is used, such as DS1833 or a similar one in TO92 package.
Standard crystal oscillator consists of xtal Q1 and capacitors C9 and C10. Used xtal is a miniature version in HC49U/S; however, the board can accomodate bigger HC49/U or HC18 packages as well.
A small I2C memory IC5 with WWW pages and scripts is connected to the processor. I2C bus is terminated by pull-up resistors R8 and R9. Their value depends on the total capacity and load of the entire bus. If the bus is used externally as well, it is recommended to terminate the other end with another pair of pull-up resistors.
Processor communicates over a serial line that is controlled by its internal UART. IC3 converts between TTL and RS232 levels. The MAX232 or its equivalent contains four TTL/RS232 converters, two RS232/TTL converters, and a 5V/+-10V converter. Built-in DC-DC converter with a charge-pump needs only four external capacitors C12 to C15 to operate. Besides pure TxD/RxD communication, the circuit supports simple RTS/CTS flow control.
Further expansions and the ISP interface utilize a PFL34connector. Version 4 introduces a new pinout!.
We are currently testing version 4 with T89C51RD2 processor and its clones by Philips. These processors are pin-compatible with DIL40 or PLCC44 versions of 89S8252 and can be substituted without any changes in hardware. However, there is a huge difference in ISP - under the same name hides an ability of booting a special program after CPU reset with special pin configuration. Boot loader can then program the flash with data received over the serial RS232 line.
LEDs D1 and D2 provide for visual communication between the user and the program inside CPU. Resistors R10 and R11 limit the current flowing through the diodes.
AT89S8252 - 8-bit Microcontroller with 8K Bytes Flash (34 pg.) [local copy]
Crystal - Embedded 10BaseT Ethernet (Gary T. Desrosiers) (47347 Bytes)
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