Web 51 - RTL8019AS Packet Driver

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Part 1 - Driver Initialization

RTL8019AS contains everything necessary to transmit and receive Ethernet packets. Packets received or ready to send are stored in the on-chip memory that is accessible from the outside through a DMA channel. The entire chip is controlled by four register banks. Register number is specified directly by addres signals A0...A4. First 16 registers are used to control and read device state. Next eight registers 16...23 are actually a single data register that serves for DMA communication. Remaining eight registers 24..31 are another single register that is used to reset the device. Register banks are not addressable directly; instead, 2 bank switching bits in register 0 are used; those are accessible from all four register banks.
A packet received or transmitted by RTL8019 consists of 60 to 1514 bytes:

Destination AddressMAC address of target node6 bytes
Source AddressMAC address of sending node6 bytes
LengthPacket length2 bytes
DATAData46 to 1500 bytes

This packet structure affects the register structure in the device. Registers that contain the destination address (EN1_PHYS) and source address (EN1_MULT) are used to control which packets are stored to the memory. In the usual configuration, device accepts packets with its own MAC as the Destination Address and with any Source Address. For transmission, packet length needs to be stored in EN0_RCNTLO (LSB) and EN0_RCNTHI (MSB).

As already mentioned, memory is accessible only through DMA channels. Usual memory structure (*) and the implied initial settings of DMA registers follow:

00h..FFhWORDconfig data from EEPROM 9346
4000h..45FFhBYTEtransmit buffer
4600h..5FFFhBYTEreceive ring buffer

Entire memory is divided into pages of 256 bytes. If a packet is shorter than a multiple of 256, it is padded to fill an entire page. Memory reserved for received packets works as a ring buffer. It is controlled by 4 registers. EN0_STARTPG and EN0_STOPPG represent the boundaries of the bufer. Assuming the usual memory configuration, their settings are:

EN0_STARTPG46h (4600h)first page address
EN0_STOPPG60h (6000h)last page address + 1

A pair of pointers, EN0_BOUNDARY and EN1_CURPAG, point into the buffer. EN0_BOUNDARY protects data not yet read from the buffer. The receiver cannot store data above this boundary. When reading data from the device, this register needs to be updated to contain the address of the page just before unread data. Second register, EN1_CURPAG, points to the location where incoming data will be stored. The following example uses packet "number" to mark used portion of memory and - for unused portions:

   46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
    -  -  -  -  -  -  -  -  -  -  -  -  -  1  1  1  2  2  2  3  3  4  4  4  -  -
   EN0_BOUNDARY = 52h   EN1_CURPAG = 5Eh

After processing three packets and receiving two other in the meantime, the situation changes:

   46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
    5  6  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  4  4  4  5  5
   EN0_BOUNDARY = 5Ah   EN1_CURPAG = 48h

Usual initial setting is:

EN0_BOUNDARY46h (4600h)1st page address
EN1_CURPAG47h (4700h)2nd page address

Register EN1_CURPAG must contain address in EN0_BOUNDARY increased by one due, to page protection. Page in EN0_BOUNDARY sets a limit. If reached by the device, memory transfer is stopped. (Wrong setting of EN1_CURPAG = ENO_BOUNDARY is even specified in AN-874 by NS). Considering this initial knowledge, the following code fragment can result:

;** Reset and init card

Pulse RSTDRV (Reset) of RTL8019AS.

        SETB    RESETBIT        ;Reset ISA bus
        ACALL   waitbus
        CLR     RESETBIT        ;End of Reset ISA bus
        ACALL   waitbus

Soft reset of RTL8019AS follows the hardware reset. It is issued by a read and subsequent write of the reset register.

        ISAIN   EN_RESET        ;Reset Port (for all pages)
        ACALL   longpause
        ISAOUTA EN_RESET        ;Reset Port (for all pages)

A stop command is sent and a delay waits for any transmission to end (well, is it really necessary after a HW reset? In any case, this way it is bulletproof.)

                                ;Remote DMA, Stop and reset the chip
        ACALL   longpause

No DMA requests, set DMA transfer length to zero.

        PORTDATA        EN0_RCNTHI,0    ;MSB Remote byte count reg
        PORTDATA        EN0_RCNTLO,0    ;LSB Remote byte count reg

Switch the device into monitor and loopback mode. No data is received from the line, only diags are possible. Set data transfer by bytes.

        PORTDATA        EN0_RXCR, ENRXCR_MON    ;RX configuration reg
                                        ;Monitor mode (no packets rcvd)
        PORTDATA        EN0_TXCR, ENTXCR_LOOP   ;TX configuration reg
                                        ;set internal loopback mode
                                        ;fifo treshold, Normal operation,
                                        ;word/byte transfer mode selection

If a 9346 EEPROM is connected, read the MAC address from it. The address is stored in "shadow" RAM starting at address 0h and can be read by regular DMA transfer. However, byte mode is not supported, bytes from this area are duplicated. When reading, only even bytes are to be processed.

        ACALL   get_board_data

Set buffer parameters.

        PORTDATA        EN_CMD, EN_PAGE0+EN_NODMA ;Remote DMA
        PORTDATA        EN0_STARTPG, RX_START_PG ;Starting page of ring buffer
                                        ;First page of RX Ring
        PORTDATA        EN0_BOUNDARY, RX_START_PG ;Boundary page of ring buffer
        PORTDATA        EN0_STOPPG,NE_STOP_PG   ;Ending page +1 of ring buffer
                                        ;End Page = Last page + 1 of RX Ring

Clear any interrupts. Mask setting does not really matter, since the circuit does not use interrupts. To make this clear, disable interrupts.

        PORTDATA        EN0_ISR, -1     ;Interrupt status reg
        PORTDATA        EN0_IMR, 0      ;Interrupt mask reg = Disable All Interrupt

Store own MAC address into the registers.

        PORTDATA        EN_CMD, EN_PAGE1+EN_NODMA ;Page 1, Remote DMA
        PORTDATA        EN1_PHYS+portind+0,my_ether+0;This board's physical enet addr
        PORTDATA        EN1_PHYS+portind+1,my_ether+1
        PORTDATA        EN1_PHYS+portind+2,my_ether+2
        PORTDATA        EN1_PHYS+portind+3,my_ether+3
        PORTDATA        EN1_PHYS+portind+4,my_ether+4
        PORTDATA        EN1_PHYS+portind+5,my_ether+5

Multicast registers contain 64 bits that enable 64 groups of multicast addresses. Individual groups of multicast addresses are determined by a CRC generator. Out of the calculated CRC of the destination MAC address, most significant 6 bits are used as an index into the above table. A '1' on the calculated position indicates that such a multicast is to be received. However, reception of multicast packets needs to be enabled in the receiver configuration register as well. By default, let's enable all multicasts.

        PORTDATA        EN_CMD, EN_PAGE1+EN_NODMA+EN_STOP ;Page 1,
                                        ;Remote DMA, Stop and reset the chip
        PORTDATA        EN1_MULT+0,0FFh ;Multicast filter mask array (8 bytes)
        PORTDATA        EN1_MULT+1,0FFh
        PORTDATA        EN1_MULT+2,0FFh
        PORTDATA        EN1_MULT+3,0FFh
        PORTDATA        EN1_MULT+4,0FFh
        PORTDATA        EN1_MULT+5,0FFh
        PORTDATA        EN1_MULT+6,0FFh
        PORTDATA        EN1_MULT+7,0FFh
                                        ;Remote DMA, Start the chip, clear reset

Initialize the pointer to the receiving buffer.

        PORTDATA        EN_CMD, EN_PAGE1+EN_NODMA+EN_STOP ;Page 1,
                                        ;Remote DMA, Stop and reset the chip
        PORTDATA        EN1_CURPAG, RX_CURR_PG  ;Current memory page = RX_CURR_PG
                                        ;Remote DMA, Start the chip, clear reset

Set transmitter mode to normal operation.

        PORTDATA        EN0_TXCR, 0     ;TX configuration reg = Normal Operation

Set receiver mode to normal operation, invalid packets rejected, broadcasts enabled, multicasts disabled.

        PORTDATA        EN0_RXCR, ENRXCR_BCST   ;RX configuration reg =
                                        ; Accept broadcasts

Clear any interrupts

        PORTDATA        EN0_ISR, -1     ;Clear the pending Interrupt /* bulletproof */

Finally, initialize internal packet driver variables to the value of the receiving buffer pointer.

        MOV     next_packet,#RX_CURR_PG
Dil 2Packet Driver RTL8019AS, Part 2

(*) Since version 1.13, memory structure has been modified to support more transmission buffers. Several details from the above description are no longer valid; however, the principle of operation remains the same.

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